// Main entry point

void main(void)
{

    
    // Call to real boot function code

    LOCAL_boot();
    
    // Jump to entry point

    DEBUG_printString("\r\nJumping to entry point at ");
    DEBUG_printHexInt(gEntryPoint);
    DEBUG_printString(".\r\n");
    APPEntry = (void(*)(void)) gEntryPoint;
    (*APPEntry)();     
}

static Uint32 LOCAL_boot(void)
{

    DEVICE_BootMode bootMode;
    
    // Read boot mode 

    bootMode = DEVICE_bootMode();
    
    if (bootMode== DEVICE_BOOTMODE_UART)
    {

        // Wait until the RBL is done using the UART.

        while((UART0->LSR& 0x40)== 0 );
    }
    
    // Platform Initialization

    if ( DEVICE_init()!= E_PASS)
    {

        DEBUG_printString(devString);
        DEBUG_printString(" initialization failed!\r\n");
        asm(" MOV PC, #0");
    }
    else
    {

        DEBUG_printString(devString);
        DEBUG_printString(" initialization passed!\r\n");
    }
    
    // Set RAM pointer to beginning of RAM space

    UTIL_setCurrMemPtr(0);
    
    // Send some information to host

    DEBUG_printString("TI UBL Version: ");
    DEBUG_printString(UBL_VERSION_STRING);
    DEBUG_printString("\r\nBooting Catalog Boot Loader\r\nBootMode = ");
    
    // Select Boot Mode

#if defined(UBL_NAND)
    {

        //Report Bootmode to host

        DEBUG_printString("NAND\r\n");
        
        // Copy binary image application from NAND to RAM

        if (NANDBOOT_copy()!= E_PASS)
        {

            DEBUG_printString("NAND Boot failed.\r\n");
            LOCAL_bootAbort();
        }
    }
#elif defined(UBL_NOR)
    {

        //Report Bootmode to host

        DEBUG_printString("NOR \r\n");
        
        // Copy binary application image from NOR to RAM

        if (NORBOOT_copy()!= E_PASS)
        {

            DEBUG_printString("NOR Boot failed.\r\n");
            LOCAL_bootAbort();
        }
    }
#elif defined(UBL_SD_MMC)
    {

        //Report Bootmode to host

        DEBUG_printString("SD/MMC \r\n");
        
        // Copy binary of application image from SD/MMC card to RAM

        if (SDMMCBOOT_copy()!= E_PASS)
        {

            DEBUG_printString("SD/MMC Boot failed.\r\n");
            LOCAL_bootAbort();
        }
    }
#else
    {

        //Report Bootmode to host

        DEBUG_printString("UART\r\n");
        UARTBOOT_copy();
    }
    
    
#endif
    
    DEBUG_printString(" DONE");
    
    UTIL_waitLoop(10000);
    
    DEVICE_TIMER0Stop();
    
    return E_PASS;
}

Uint32 DEVICE_init()
{

    Uint32 status = E_PASS;
    
    // Mask all interrupts
    AINTC->INTCTL= 0x4;
    AINTC->EABASE= 0x0;
    AINTC->EINT0= 0x0;
    AINTC->EINT1= 0x0;        
    
    // Clear all interrupts
    AINTC->FIQ0= 0xFFFFFFFF;
    AINTC->FIQ1= 0xFFFFFFFF;
    AINTC->IRQ0= 0xFFFFFFFF;
    AINTC->IRQ1= 0xFFFFFFFF;
    
#ifndef SKIP_LOW_LEVEL_INIT
    
    POR_RESET();
    
    // System PSC setup - enable all
    DEVICE_PSCInit();
    
    DEVICE_pinmuxControl(0,0xFFFFFFFF,0x00FD0000);// All Video Inputs

    DEVICE_pinmuxControl(1,0xFFFFFFFF,0x00145555);// All Video Outputs

    DEVICE_pinmuxControl(2,0xFFFFFFFF,0x000000DA);// EMIFA

    DEVICE_pinmuxControl(3,0xFFFFFFFF,0x00180000);// SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs

    DEVICE_pinmuxControl(4,0xFFFFFFFF,0x55555555);// MMC/SD0 instead of MS, SPI0

    
    GPIO->DIR02&= 0xfeffffff;
    GPIO->CLRDATA02= 0x01000000;
    
    // System PLL setup
    if (status== E_PASS) status|= DEVICE_PLL1Init(PLL1_Mult);
    
    // DDR PLL setup
    if (status== E_PASS) status|= DEVICE_PLL2Init();
    
    // DDR2 module setup
    if (status== E_PASS) status|= DEVICE_DDR2Init();
#endif
    
    // AEMIF Setup
    if (status== E_PASS) status|= DEVICE_EMIFInit();
    
    // UART0 Setup
    if (status== E_PASS) status|= DEVICE_UART0Init();
    
    // TIMER0 Setup
    if (status== E_PASS) status|= DEVICE_TIMER0Init();
    
    // I2C0 Setup
    if (status== E_PASS) status|= DEVICE_I2C0Init();
    
    return status;
}

void DEVICE_PSCInit()
{
    
    unsigned char i=0;
    unsigned char lpsc_start;
    unsigned char lpsc_end,lpscgroup,lpscmin,lpscmax;
    unsigned int PdNum= 0;
    
    lpscmin =0;
    lpscmax =2;
    
    for(lpscgroup=lpscmin; lpscgroup<=lpscmax; lpscgroup++){

        if(lpscgroup==0)
        {

            lpsc_start = 0;// Enabling LPSC 3 to 28 SCR first

            lpsc_end = 28;
        }
        else if(lpscgroup== 1){
/* Skip locked LPSCs [29-37] */
            lpsc_start = 38;
            lpsc_end = 47;
        } else{

            lpsc_start = 50;
            lpsc_end = 51;
        }
        
        //NEXT=0x3, Enable LPSC's
        for(i=lpsc_start; i<=lpsc_end; i++){

            PSC->MDCTL[i]|= 0x3;
        }
        
        //Program goctl to start transition sequence for LPSCs
        PSC->PTCMD=(1<<PdNum);
        
        //Wait for GOSTAT = NO TRANSITION from PSC for Pdomain 0
        while(!(((PSC->PTSTAT>> PdNum)& 0x00000001)== 0));
        
        //Wait for MODSTAT = ENABLE from LPSC's
        for(i=lpsc_start; i<=lpsc_end; i++){

            while(!((PSC->MDSTAT[i]& 0x0000001F)== 0x3));             
        }    
    }     
    
}

Uint32 DEVICE_DDR2Init()
{

    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);
    
    SYSTEM->VTPIOCR=(SYSTEM->VTPIOCR)& 0xFFFF9F3F;
    
    // Set bit CLRZ (bit 13)
    SYSTEM->VTPIOCR=(SYSTEM->VTPIOCR)| 0x00002000;
    
    // Check VTP READY Status
    while( !(SYSTEM->VTPIOCR& 0x8000));
    
    // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
    //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; 

    // Set bit LOCK(bit7) and PWRSAVE (bit8)
    SYSTEM->VTPIOCR=SYSTEM->VTPIOCR| 0x00000080;
    
    // Powerdown VTP as it is locked (bit 6)
    // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
    SYSTEM->VTPIOCR=SYSTEM->VTPIOCR| 0x00004040;
    
    // Wait for calibration to complete 
    UTIL_waitLoop( 150 );
    
    // Set the DDR2 to synreset, then enable it again
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET);
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);
    
    DDR->DDRPHYCR= 0x000000C5;   
    DDR->SDBCR= 0x08D34832;        //Program SDRAM Bank Config Register
    DDR->SDBCR= 0x0853C832;    
    DDR->SDTIMR=0x3C934B51;        //Program SDRAM Timing Control Register1
    DDR->SDTIMR2=0x4221C72;        //Program SDRAM Timing Control Register2
    DDR->PBBPR= 0x000000FE;   
    DDR->SDBCR= 0x08534832;        //Program SDRAM Bank Config Register   
    DDR->SDRCR= 0x00000768;        //Program SDRAM Refresh Control Register
 
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET);
    DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE);
    
    return E_PASS;
}

void DEVICE_LPSCTransition(Uint8 module, Uint8 domain, Uint8 state)
{

    // Wait for any outstanding transition to complete
    while ((PSC->PTSTAT)&(0x00000001<< domain));
    
    // If we are already in that state, just return
    if (((PSC->MDSTAT[module])& 0x1F) == state)return;
    
    // Perform transition
    PSC->MDCTL[module]=((PSC->MDCTL[module])&(0xFFFFFFE0))|(state);
    PSC->PTCMD|=(0x00000001 << domain);
    
    // Wait for transition to complete
    while ((PSC->PTSTAT)&(0x00000001<< domain));
    
    // Wait and verify the state
    while (((PSC->MDSTAT[module])& 0x1F) != state);    
}

Uint32 DEVICE_EMIFInit()
{
    
    AEMIF->AWCCR= 0xff;   
    AEMIF->A1CR= 0x40400204;  
    AEMIF->NANDFCR|= 1;  
    AEMIF->A2CR= 0x00a00505;
    
    return E_PASS;   
}

Uint32 DEVICE_UART0Init()
{
    
    UART0->PWREMU_MGNT= 0;// Reset UART TX & RX components

    UTIL_waitLoop( 100 );
    
    UART0->MDR= 0x0;
    UART0->DLL= 0xd;// Set baud rate    
    UART0->DLH= 0;
     
    UART0->FCR= 0x0007;// Clear UART TX & RX FIFOs
    UART0->FCR= 0x0000;// Non-FIFO mode
    UART0->IER= 0x0007;// Enable interrupts

    UART0->LCR= 0x0003;// 8-bit words
    // 1 STOP bit generated,
    // No Parity, No Stick paritiy,
    // No Break control
 
    UART0->MCR= 0x0000;// RTS & CTS disabled,
    // Loopback mode disabled,
    // Autoflow disabled
 
    UART0->PWREMU_MGNT= 0xE001;// Enable TX & RX componenets
 
    return E_PASS;
}

Uint32 DEVICE_TIMER0Init()
{

    // Put timer into reset
    TIMER0->EMUMGT_CLKSPD= 0x00000003;
    TIMER0->TCR= 0x00000000;
    
    // Enable TINT0, TINT1 interrupt
    TIMER0->INTCTL_STAT= 0x00000001;
    
    // Set to 64-bit GP Timer mode, enable TIMER12 & TIMER34
    TIMER0->TGCR= 0x00000003;
    
    // Reset timers to zero 
    TIMER0->TIM12= 0x00000000;
    TIMER0->TIM34= 0x00000000;
    
    // Set timer period (5 second timeout = (24000000 * 5) cycles = 0x07270E00) 
    TIMER0->PRD34= 0x00000000;
    TIMER0->PRD12= 0x07270E00;
    
    return E_PASS;
}